1. Field of the Invention
The present invention relates to a display device using, for example, a liquid crystal material; and in particular, a liquid crystal display device having a sufficiently small deviation among threshold characteristics of thin film transistors which are respectively provided with respect to a plurality of pixel electrodes.
2. Description of the Related Art
A liquid crystal display device using a thin film transistor (hereinafter, referred to as a "TFT") as a switching element will be described with reference to FIG. 6.
As shown in FIG. 6, a liquid crystal display device 500 includes a plurality of TFTs 523, pixel capacitors 522, gate signal lines 524, source signal lines 526, storage capacitor lines 525, and driving circuits 580 and 590. The TFTs 523 and the pixel capacitors 522 are both provided in a matrix, i.e., in rows and columns. The pixel capacitors 522 each include a storage capacitor 520 and the liquid crystal capacitor 530.
The plurality of gate signal lines 524 extends in a first direction (i.e., row direction), and the plurality of source signal lines 526 extends in a second direction (i.e., column direction) perpendicular to the first direction. Each of gate signal lines 524 is connected to gate electrodes 524a of the TFTs 523 arranged in the corresponding row. Each of source signal lines 526 is connected to source electrodes 505 of the TFTs 523 arranged in the corresponding column.
For simplicity, the following description will be given regarding one pixel area.
A drain electrode 506 of the TFT 523 is connected to a pixel electrode, which is one of electrodes of the liquid crystal capacitor 530, and also connected to one of two electrodes of the storage capacitor 520. The other electrode of the storage capacitor 520 is connected to the storage capacitor line 525 and further to a counter electrode provided on a counter substrate (not shown).
The gate signal line 524 is supplied with a scanning signal by the driving circuit 580, and the source signal line 526 is supplied with a video signal by the driving circuit 590. The TFT 523 supplies the pixel capacitor 522 with a video signal sent from the source signal line 526 in accordance with the scanning signal supplied by the gate signal line 524.
With reference to FIGS. 7A, 7B and 8, a pixel area in the liquid crystal display device 500 will be described in detail.
FIG. 7A is a view illustrating a planar structure of one pixel area of the liquid crystal display device 500, and FIG. 7B is an enlarged view of part D in FIG. 7A. FIG. 8 is a cross-sectional view of the one pixel area of the liquid crystal display device 500 shown in FIG. 7A taken along line 8--8 in FIG. 7A.
As shown in FIG. 8, the liquid crystal display device 500 includes an active matrix substrate 500a, a counter substrate 500b, and a liquid crystal layer 517 interposed therebetween.
The active matrix substrate 500a includes a light-transmissive insulative plate 501. The gate signal line 524, a gate electrode 524a branched from the gate signal line 524, and a storage capacitor line 525 are provided on the insulative plate 501. A gate insulating layer 503 is provided on the insulative plate 501 so as to cover the gate signal line 524, the gate electrode 524a, and the storage capacitor line 525.
A semiconductor layer 504 is provided on the gate insulating layer 503 so as to overlap the gate electrode 524a. The source electrode 505 and the drain electrode 506, each formed of an n.sup.+ -Si layer, are provided on the semiconductor layer 504. The source electrode 505 and the drain electrode 506 have a gap therebetween on the semiconductor layer 504. The TFT 523 includes the gate electrode 524a, the semiconductor layer 504, the source electrode 505 and the drain electrode 506.
An ITO layer 507a and a metal layer 508a are provided sequentially in this order on the source electrode 505. The ITO layer 507a and the metal layer 508a act together as a source leading electrode. The ITO layer 507a and the metal layer 508a extend on the gate insulating layer 503 in a direction perpendicular to the gate signal line 524, so as to act as the source signal line 526.
An ITO layer 507b and a metal layer 508b are provided sequentially in this order on the drain electrode 506. The ITO layer 507b and the metal layer 508b act together as a drain leading electrode. The ITO layer 507b extends to an area below a through-hole 510 (described below), so as to act as a leading electrode 507.
An interlayer insulating layer 509 is provided on the gate insulating layer 503 so as to cover the TFT 523, the source signal line 526 and the leading electrode 507. A pixel electrode 511 formed of a transparent conductive layer is provided on the interlayer insulating layer 509. An alignment layer 516 is provided on the interlayer insulating layer 509 so as to cover the pixel electrode 511.
The interlayer insulating layer 509 has a through-hole 510 formed therethrough. The pixel electrode 511 is electrically connected to the leading electrode 507 through the through-hole 510. Due to such a structure, the pixel electrode 511 and the drain electrode 506 of the TFT 523 are electrically connected to each other.
The position of the through-hole 510 corresponds to the storage capacitor line 525 provided on the insulative plate 501. A portion where the storage capacitor line 525, the gate insulating layer 503 and the leading electrode 507 overlap one another acts as the storage capacitor 520.
The counter substrate 500b includes a light-transmissive insulative plate 512. A color filter 514 and a light blocking layer 513 are provided on the insulative plate 512. A counter electrode 515 is provided on the color filter 514 and the light blocking layer 513. An alignment layer 516 is provided on the counter electrode 515.
In the above-described structure, the interlayer insulating layer 509 is provided between the gate signal line 524/source signal line 526 and the pixel electrode 511. Accordingly, the pixel electrode 511 can overlap the gate signal line 524 and the source signal line 526. Such a structure is disclosed in, for example, Japanese Laid-Open Publication No. 58-172685. It is known that such a structure has an effect of improving the aperture ratio. It is also known that this structure has an effect that the pixel electrode blocks the electric field caused by the gate signal line and the source signal line, thereby suppressing defective alignment of liquid crystal molecules.
In order to realize the above-described structure in which the pixel electrode overlaps the gate electrode and the source electrode, it is necessary to reduce the parasitic capacitance generated between the gate electrode/source electrode and the pixel electrode.
The parasitic capacitance has a serious adverse influence referred to as "shadowing" on the display quality in an active matrix liquid crystal display device. Shadowing can be reduced by adopting a certain driving method, but it is preferable to reduce the parasitic capacitance itself in order to solve the problem substantively.
As a solution of such a problem, the interlayer insulating layer is formed of, for example, acrylic resins, polyimide, benzocyclobutene, and fluorocarbon resins. These materials realize formation of an insulating layer having a low dielectric constant (specific dielectric constant of equal to or less than that of a silicon oxide layer) and a thickness of about 2 to 5 .mu.m. However, such an insulating layer contains metal ions as impurities in the order of several hundred parts per billion. The metal impurities cause deviation in the threshold voltage among the TFTs and thus increase the deviation in the characteristics of the resultant liquid crystal display devices.